The present invention relates to a semiconductor device and a technique for manufacturing the same. Particularly, the present invention is concerned with a technique which is effectively applicable to a multi-chip module (MCM) with plural types of semiconductor chips of different terminal pitches mounted on a wiring substrate.
As a measure for increasing the capacity of memory LSIs such as flash memory and DRAM (Dynamic Random Access Memory), various memory module structures have been proposed in which-semiconductor chips (memory chips) with such memory LSIs formed thereon are stacked and sealed in a single package.
For example, Japanese Published Unexamined Patent Application No. Hei 4(1992)-302164 discloses a package structure wherein plural semiconductor chips of the same function and same size are stacked stepwise through an insulating layer within a single package and bonding pads exposed to stepped portions of the semiconductor chips and inner leads of the package are electrically connected together through wires.
In Japanese Published Unexamined Patent Application No. Hei 11(1999)-204720 there is disclosed a package structure wherein a first semiconductor chip is mounted on an insulating substrate through a thermocompression bonding sheet, a second semiconductor chip having an external size smaller than that of the first semiconductor chip is mounted on the first semiconductor chip through an insulating sheet, bonding pads of the first and second semiconductor chips and a wiring layer on the insulating substrate are electrically connected together through wires, and the first and second semiconductor chips and the wires are sealed with resin.
Also known is a technique called Wafer Level CSP (Chip Size Package) or Wafer Process Package (WPP) wherein solder bumps are arranged in an array form on a main surface of a semiconductor chip and bonding pads and the solder bumps are electrically connected together through wires formed of Cu (copper) for example, thereby making the pitch of connecting terminals (solder bumps) wider than that of the bonding pads. With this technique, the terminal pitch of the semiconductor chip can be substantially widened, so that even without using an expensive build-up substrate with narrowed line and space of wires, it is possible to fabricate a memory module with use of a less expensive resin substrate having a wide wiring pitch. As to Wafer Level CSP, related descriptions are found, for example, in xe2x80x9cElectronics Mounting Technique: 2000 Extra Edition,xe2x80x9d pp. 81 to 113, published by Kabushiki Kaisha TECHNICAL RESEARCH COUNCIL (May 28, 2000), and also in International Patent Publication WO99/23696.
The inventors in the present case are developing a multi-chip module with plural semiconductor chips (hereinafter referred to simply as xe2x80x9cchipxe2x80x9d) mounted within a single package.
According to the multi-chip module now under our development, chips with memory LSIs such as DRAM (Dynamic Random Access Memory) and flash memory formed thereon and a chip with a high-speed microprocessor (MPU: microprocessing unit) formed thereon are sealed within a single resin package, whereby it is intended to implement a system more versatile than the conventional memory module wherein plural memory chips are sealed with resin.
The present inventors are now making a study about mounting chips on a less expensive resin substrate having a wide wiring pitch for the purpose of reducing the cost of manufacturing the multi-chip module. To this end it is necessary to substantially widen the terminal pitch of each chip by utilizing the foregoing Wafer Level CSP technique.
On this regard, there arises no problem in the case of a chip having a relatively small number of terminals like a chip with memory LSI such as DRAM or flash memory formed thereon, but in the case of a chip having a large number of terminals like a chip with a microprocessor formed thereon, a limit is encountered in substantially widening the terminal pitch of the chip even by utilizing the Wafer Level SCP technique.
For example, the minimum pitch of wires capable of being formed on an inexpensive resin substrate by utilizing the wiring substrate manufacturing technique available at present is 0.5 mm. On the other hand, in the case where 0.5 mm pitch solder bumps are to be formed by utilizing the wafer process package technique on a DRAM having a chip size of 4.66 mmxc3x978.22 mm and having 64 pins as terminals and a terminal pitch of 0.08 mm, there arises no problem because a maximum of 128 pins of solder bumps can be formed. However, when 0.5 mm pitch solder bumps are to be formed on, for example, a microprocessor having a chip size of 6.84 mmxc3x976.84 mm and having 256 pins as terminals and a terminal pitch of 0.08 mm, there can be formed only 169 pins of solder bumps even as a maximum number. Therefore, if this chip is to be mounted in accordance with a flip-chip method, it is necessary to use an expensive build-up substrate having a wiring pitch of 0.4 mm or less.
It is an object of the present invention to provide a technique which can reduce the cost of manufacturing a multi-chip module with plural types of chips different in terminal pitch mounted on a wiring substrate.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
A typical invention out of those disclosed herein will be outlined below.
A multi-chip module according to the present invention comprises a wiring substrate with plural wires and plural bonding pads formed on a main surface thereof, one or plural first semiconductor chips mounted in a first area of the main surface of the wiring substrate and connected electrically to the wires through plural bump electrodes, and a second semiconductor chip stacked on the first semiconductor chip(s) and connected electrically to the bonding pads through plural wires, wherein a terminal pitch of the second semiconductor chip is narrower than that of the first semiconductor chip(s).